A Novel Concept - CPU with a one gate ALU

This was something I wrote a few years ago, and I found it again just the other day . Y'know, like your cloud drive becomes the bottom of the closet kinda thing? A Novel Concept…

Here's an idea for a logic controller that uses only one mnemonic! It's based on the fact that any sequential logic can be expressed as compound logic, and any compound logic can be expressed in "NAND" gates. Each instruction is in fact 3 register addresses:

A

B

X

So the function of each and every instruction is X=A.B. The architecture is similar to a PLC: Registers are 1 bit memories, and the scan cycle is:

1. Read Inputs into Registers

2. Execute Logic

3. Write Outputs from Registers

4. Check for Programming Device Interrupt

5. Goto Step 1

The Program memory is a printer buffer, with each read instruction generating a write to put a copy back in. A counter keeps track of where execution must stop and I/O servicing start.

The format used for notation is A-B-X - an instruction such as "start OR latch" becoming a sequence:

start-start-nstart

invert start

latch-latch-nlatch

invert latch

nstart-nlatch-nresult

NOR= NAND of the inverses

Some basic logic:

Dummy:

A dummy register, whose contents is considered irrelevant is used instead of a "NOP" instruction, as in D-D-D

Invert:

Not-A can be done 2 ways: A-A-X or 1-A-X, where 1 is achieved by always having a register with a 1 in it, called "SET"

NAND:

A-B-X

X=A.B

AND:

A-B-NX

NX-NX-X

X=A.B

OR:

A-A-NA

B-B-NB

NA-NB-X

X=A+B

NOR:

A-A-NA

B-B-NB

NA-NB-NX

NX-NX-X

X=A+B

XOR:

A-A-NA

B-B-NB

A-NB-C

NA-B-D

C-D-X

X=A(+)B

XNOR:

A-A-NA

B-B-NB

A-B-C

NA-NB-D

C-D-X

X=A(+)B

R-S Latch:

NRESET-Q-NQ

NOTE THAT NRESET & NSET ARE

NSET-NQ-Q

ACTIVE LOW, AND ALSO, IF NSET

GOES LOW, FOR 1 CYCLE OF THE

PROGRAM, BOTH Q AND NQ ARE HIGH.

Q-Q-NQ

<---- font="">

TO AVOID THIS, USE THIS LINE

AFTER THE LAST.